After finishing the ALU, I started thinking about how I was going to shuttle data around, and where I was going to store it. This process evolved pretty organically, with the different internal registers and their routing sort of building on top of each other.
I knew to begin with I wanted at a bare minimum: - An accumulator register to store the result of operations - A program counter to store the location of the current instruction - Address registers to store the current location I was pointing to in memory.
While I don't have a ton of personal experience programming for older 8 bit processors, I'd been looking quite a bit at the design of the Z80 and 6502 processors, and I knew the 6502 also had the extra X and Y index registers. I figured two extra general purpose registers would be reasonable to implement in real hardware, so I folded them into the design. I had a vague idea that in the future I might be able to use the X and Y registers as a 16 bit pair with which to do pointer indirection, sort of like the Z80 has in the IX and IY register pairs.
I didn't know quite what I was going to do with the bus structure, but knew that the registers would need to be able to feed themselves into the ALU and would need to be written to from the ALU, so I decided to start working around that, just knowing that the register file would need at least one input and two outputs. I started by plopping down my three general purpose registers, and wired them up to clock and reset lines.
After that, I wired them through buffers and a decoder, so one and only one of them could output to the left operand of the ALU.
And simply did the same for the right operand.
That... that was pretty straightforward, actually.
Now we need to handle the input side of register file so we can write the results of our calculations back out somewhere.
I left the first output of the decoder unconnected, so that we could elect to not write to any register at all if we didn't want to.
Once we plop down this register file circuit we just completed, our CPU starts to take a little shape!
Before we bounce, I want to take a look at the design we have so far, and evaluate if this is realistic to build in real life. With the design we have, we're going to need one register ic and two buffer ics for each general purpose register. That's 3 × 3 = 9 ics, plus two more for the decoders. I think this is pretty reasonable so far. We still need to add a program counter, at least, and I have visions of a dedicated stack pointer as well, but